Versalogic Lead Generation Campaign 2014

Versalogic Whitepaper Campaign

Whitepaper #1: MythBuster – “Extended Temperature” Embedded Computers

When integrating Single Board Computers (SBCs) into industrial, military, and aerospace systems, engineers typically specify an extended temperature range SBC for their embedded computing requirements. The “extended temperature” designation theoretically assures that the SBC will perform reliably in extreme temperature environments. If an SBC supplier labels their product as “extended temperature”, then it will be reliable in the field. Right?

Well, that depends. Are there commercial grade components being used on the board? Is the board 100% tested over the full temperature range? How does the SBC supplier define their extended temperature range?

Download this MythBuster technical paper to learn how to find a truly reliable solution for your extended temperature range embedded computing needs.

Whitepaper #2: The Invisible Foe – Understanding and Controlling ESD Damage

Electrostatic discharge (ESD) is indeed the “invisible foe” of electronic product quality and reliability. ESD includes spectacular electric sparks, but also less dramatic forms which may be neither seen nor heard, yet still are large enough to cause damage to sensitive electronic devices. These unseen events can be extremely costly. ESD damage lowers production yields, increases warranty rework, causes higher inventory requirements, and lowers customer satisfaction. According to industry experts, high tech OEMs lose at least 4% to 6% of annual gross sales due to ESD every year. Read this white paper and learn how you can help your organization identify potential sources of ESD loss, establish effective ESD controls, and improve product reliability.

Trenton Systems Lead Generation Campaign 2014

Whitepaper: Optimizing PCIe 3.0 Backplane Designs for Performance and Reliability

PCIe 3.0 is the latest release of the ubiquitous PCI Express high-speed peripheral interconnect standard that provides 8GT/s of interconnect bandwidth which doubles the PCIe 2.0 bit rate while preserving full compatibility with all existing software and mechanical interfaces.

At the backplane design level, the doubling of data transfer rates in PCIe 3.0 means much higher signal speeds and additional signal integrity challenges. Important design issues include placement of discrete components, the length of the traces that connect these components, and the utilization of active vs. passive signal management methodologies.

This white paper explores the issues that are critical for achieving optimal PCIe 3.0 backplane design as well as the performance advantages and system configurability benefits that can be achieved through a proper PCIe 3.0 backplane implementation.
Topics in this whitepaper:

  • PCIe 3.0 Enhanced Performance Opportunities
  • High-Efficiency Encoding Scheme in PCIe 3.0
  • Enhanced Transaction Layer Features
  • Active Equalization Capabilities
  • Active vs. Passive Approach to Design
  • Jitter Control, Impedance and Signal Loss
  • Real World Deployment Issues

The first 100 registrants enter to win your choice of a
GoPro HERO3+: Black Edition or an iPad Air.

Drawing will be held at a time TBD and the winner will be notified with their registered email address. Choice between prizes will be up to the recipient, and mailed via postal mail. For more information, Visit – or Call – 770.287.3100