Whitepaper: Optimizing PCIe 3.0 Backplane Designs for Performance and Reliability
PCIe 3.0 is the latest release of the ubiquitous PCI Express high-speed peripheral interconnect standard that provides 8GT/s of interconnect bandwidth which doubles the PCIe 2.0 bit rate while preserving full compatibility with all existing software and mechanical interfaces.
At the backplane design level, the doubling of data transfer rates in PCIe 3.0 means much higher signal speeds and additional signal integrity challenges. Important design issues include placement of discrete components, the length of the traces that connect these components, and the utilization of active vs. passive signal management methodologies.
This white paper explores the issues that are critical for achieving optimal PCIe 3.0 backplane design as well as the performance advantages and system configurability benefits that can be achieved through a proper PCIe 3.0 backplane implementation.
Topics in this whitepaper:
- PCIe 3.0 Enhanced Performance Opportunities
- High-Efficiency Encoding Scheme in PCIe 3.0
- Enhanced Transaction Layer Features
- Active Equalization Capabilities
- Active vs. Passive Approach to Design
- Jitter Control, Impedance and Signal Loss
- Real World Deployment Issues
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Drawing will be held at a time TBD and the winner will be notified with their registered email address. Choice between prizes will be up to the recipient, and mailed via postal mail. For more information, Visit – www.TrentonSystems.com or Call – 770.287.3100